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Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-11.0')
-rw-r--r--metadata/md5-cache/sci-electronics/iverilog-11.04
1 files changed, 2 insertions, 2 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-11.0 b/metadata/md5-cache/sci-electronics/iverilog-11.0
index 0f49af47244a..21027c32491c 100644
--- a/metadata/md5-cache/sci-electronics/iverilog-11.0
+++ b/metadata/md5-cache/sci-electronics/iverilog-11.0
@@ -1,4 +1,4 @@
-BDEPEND=dev-util/gperf sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.5:1.16 ) || ( >=sys-devel/autoconf-2.72-r1:2.72 >=sys-devel/autoconf-2.71-r6:2.71 ) >=sys-devel/libtool-2.4.7
+BDEPEND=dev-util/gperf sys-devel/bison app-alternatives/lex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.5:1.16 ) || ( >=sys-devel/autoconf-2.72-r1:2.72 >=sys-devel/autoconf-2.71-r6:2.71 ) >=sys-devel/libtool-2.4.7
DEFINED_PHASES=install prepare
DEPEND=sys-libs/readline:= sys-libs/zlib
DESCRIPTION=A Verilog simulation and synthesis tool
@@ -11,4 +11,4 @@ RDEPEND=sys-libs/readline:= sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/steveicarus/iverilog/archive/v11_0.tar.gz -> iverilog-11.0.tar.gz
_eclasses_=autotools 5f729b9cb10d5eda573cd604c93c6dc5 gnuconfig b6b3e92f8b8c996400074b5f61a59256 libtool 9d3a9a889a6fa62ae794f817c156491b multilib c19072c3cd7ac5cb21de013f7e9832e0 toolchain-funcs e56c7649b804f051623c8bc1a1c44084
-_md5_=bdd5d0b47bcf1d8e44ddf39610817edb
+_md5_=319f2f7ac50417a0132f534fadccb3c4