diff options
Diffstat (limited to 'dev-qt/qtbase')
| -rw-r--r-- | dev-qt/qtbase/Manifest | 3 | ||||
| -rw-r--r-- | dev-qt/qtbase/files/qtbase-6.7.2-haswell-no-rdrnd.patch | 100 | ||||
| -rw-r--r-- | dev-qt/qtbase/qtbase-6.7.2-r5.ebuild (renamed from dev-qt/qtbase/qtbase-6.7.2-r4.ebuild) | 1 |
3 files changed, 103 insertions, 1 deletions
diff --git a/dev-qt/qtbase/Manifest b/dev-qt/qtbase/Manifest index 16854799bdea..e86cb880ef45 100644 --- a/dev-qt/qtbase/Manifest +++ b/dev-qt/qtbase/Manifest @@ -5,12 +5,13 @@ AUX qtbase-6.6.3-gcc14-avx512fp16.patch 470 BLAKE2B 616b4fdcee6819a0ca4de1220f75 AUX qtbase-6.7.2-CVE-2024-39936.patch 7171 BLAKE2B d1b6e9a35e35f1e6b3e7a7c975fb6719b8594ee5f3212bc18bfe4a1990d70424a682071551c5971d62d6351a38e36b6f4c4acb9241af1ad2e64ec604ca440394 SHA512 cd6b48ebe7c1dc1224a54f0d32845e598223a3c40c6da11b4639646fb073c6b5a2e54d9625ba0413afb876a83c2d50bdf616f4876154fb33fa941d6cbf053291 AUX qtbase-6.7.2-float16-sse2.patch 1773 BLAKE2B c5b8bb7065db6186d81fb9267235327eba698c096d3e8051a2671d4655ada21ff063b297b00b8da098bb07b6a4abc9fb42fb7652e9de8aa759a349f8f1e58afc SHA512 af4b3c014ce86de25c02d7846ff0e354762513313d353971e6259da1dea20d6bc5ae7fb475469d29c3251d4e9e6446afda8b21086df50ba1108083d112bbfe73 AUX qtbase-6.7.2-gcc15-odr.patch 1162 BLAKE2B 640688d21fb70ce67378e0f8ac5ddac12b657a9802c0f2e524e6c210cf055955cda41300dd792949541e085d5e8a7ef19dcceaa36f6f73da651f89e88dab2ff4 SHA512 3dd8f26d02fb11075f97b3284e8c0ed1bcff5feafc6535026078dc5b38ed106ae144c18db1fff502b1cebb06761f55d995a8e31c8a6b701f08d21fdbb170bba1 +AUX qtbase-6.7.2-haswell-no-rdrnd.patch 4826 BLAKE2B 24071787ae48acec749e59cd7acc35c0137229dfb585bd05761e1b2fa2740f7df77161bf3a9fe2c8fb4430afdf1c610fdea42969691662c6d7c4e1e949865098 SHA512 a2c3fb782cc942db173135cffca3d24eb83dd2bc39e55f0cb2dae621297c22673ee6dfc5224c7237f8078faf036e692d41e119d78e5ccfd5d85ae8654d1009f8 AUX qtbase-6.7.2-qcontiguouscache.patch 310 BLAKE2B 736663ba1d07285fb5bb6b050b88cec9beaf20fdb7815fe1c2008872c6d076e04c76ae1b54c930c7096043ceba7285e4ac85c46c67720afb105a0647d0baa200 SHA512 81d7942275695fa82a2794792f5e4a5d6b7aa93515017146a55c52f0ba3edb9f2f4252f317978bfaf52856ef1c3295ad4fe5c21a55502c8c8b22f305a0753bb6 AUX qtbase-6.7.2-qwindowprivate-crash.patch 1337 BLAKE2B 1d8e354dc0db89744073bf555263129904592fb7c05b315713a21eae94b52a4b847dae906700cc5551fa21f828373ed044903dd10e8b86670b9296aa2009a3a3 SHA512 30e54110b9351aa2f7614a416b1fdf0d192a42386bdc5e75bd91fa2ecb98c48066b4e3858f97e00abbcbf2ddd5e90eab1594e285434d083215eaa34463dfa65b AUX qtbase-6.8.0-qcontiguouscache.patch 526 BLAKE2B b701f92d8365e8408a2ff79c812c397ac0042aa6b6316cf167a7877d48044ffaa0d2683fa27ffcbe80c8e74f8ff0c8af220b927889e83340c6b5325b1fbf16ab SHA512 19f33f2dd856c8328b9175458250929f3da34cde179d5f52ec1982e5e5f1772412f2541e146763a6258ce3377e0b624f07926fe4af56de7364c34835151b8995 DIST qtbase-everywhere-src-6.7.2.tar.xz 49364504 BLAKE2B b48b8a8decafe3262d459b9446c25561851fef88b3316107c2909f5964e8122a558b5501a3e59667bdf4776d36ea5ba0d9f227538c45c1f8e94fbc8fff4244a6 SHA512 eb4b2f1fb02ab0ed5508d32449e140778278ff1a619cfcae14920b276b5c46e01a566d73fb8f84cf2cfc81e19cb11e53ab500df6b27d12ab875aa8c07bd15d6b DIST qtbase-everywhere-src-6.8.0-rc.tar.xz 49816580 BLAKE2B 321aebf3404d080d09148ac68c173923e7d3d468beaccb4e036ba099786e4fb0e3e9b044a2317ad03f490fd1c72ad1ee2f0c926b96d0c312cad79109da362238 SHA512 04d003815d493bba1b0d609b61aa39343906886e15a00bae36e95011684dbece400c353b72c5167fac70dfcdc31ec53813afb0294564d996fe8bc4c24fe0e3c2 -EBUILD qtbase-6.7.2-r4.ebuild 10267 BLAKE2B 86090d41433852a3cca5e3e1c893d9c94d44b2e0783194779c9f501f8f32d5001fb2fb8786eac4991b3ae4ad3db97320fb245669d65e8213178432ae02570ff1 SHA512 28a2ea55c6a3e5a99d7baff53d787983af9b288b515fbf9f29d71b4ef885a6b363d35e2c970f919653ebb98472603a0d59ba54353096698e37ef1a4358cd5f5e +EBUILD qtbase-6.7.2-r5.ebuild 10317 BLAKE2B 92c1b6a9bea4277229f80a96c356de139d7809daa37cf7efaa7bb6e9ceba7ddb53dcc7dbe16919d800b379b9bf896c79de5b56378a593cce914c4ab74c433048 SHA512 19d1666bc8022a6c2aa8bf0f6692a9eadce471655876d7930f2043fc9b02d1fbb21ce81f9dd8553167f51eb2b62d36f9baec69753b73cd76e4de833faa7da14b EBUILD qtbase-6.7.9999.ebuild 10017 BLAKE2B 2d8d281b680059466fd16962380e338dcd115d2e3c77cfc88e0ceae1337f49ede09534bb8f923108bce66a3b993a753744ca99a3c2d9e27d080115a3e1ef6f23 SHA512 f6b94592da24dee07c3a488d45c2c18aa421c47c65180cd954f9252835bdc0109bc9de61b72be9842ceef7b93f30f5c1fc1a0f1006a3bb4e0cfd1246625efdea EBUILD qtbase-6.8.0_rc.ebuild 10554 BLAKE2B 64b0c95b5763f5e772e643cde8b11118034ddc303707e8c8b2cc7086f2b36f21ccff7b225d5a6aa818c65a63aa89d57127cbb985a486842f6746e0da2b85a0bb SHA512 bb42ddd44da538c8b229d150a02692524065afafe347268c0f2cf1e77cb8a8b310f9d8bac110dce3063d0203c7b74d4fa52b5a72b5eb8cc48e3b00d185d7df11 EBUILD qtbase-6.8.9999.ebuild 10554 BLAKE2B 64b0c95b5763f5e772e643cde8b11118034ddc303707e8c8b2cc7086f2b36f21ccff7b225d5a6aa818c65a63aa89d57127cbb985a486842f6746e0da2b85a0bb SHA512 bb42ddd44da538c8b229d150a02692524065afafe347268c0f2cf1e77cb8a8b310f9d8bac110dce3063d0203c7b74d4fa52b5a72b5eb8cc48e3b00d185d7df11 diff --git a/dev-qt/qtbase/files/qtbase-6.7.2-haswell-no-rdrnd.patch b/dev-qt/qtbase/files/qtbase-6.7.2-haswell-no-rdrnd.patch new file mode 100644 index 000000000000..0427315d69d5 --- /dev/null +++ b/dev-qt/qtbase/files/qtbase-6.7.2-haswell-no-rdrnd.patch @@ -0,0 +1,100 @@ +https://bugreports.qt.io/browse/QTBUG-129193 +https://forums.gentoo.org/viewtopic-t-1170690.html +https://forums.gentoo.org/viewtopic-t-1169619.html +https://codereview.qt-project.org/c/qt/qtbase/+/593073 +From: Thiago Macieira <thiago.macieira@intel.com> +Date: Mon, 23 Sep 2024 13:44:31 -0700 +Subject: [PATCH] qsimd_x86: disable the requirement that CPUs must have RNGs + +Intel CPUs have had this since 2013 (Ivy Bridge), but some older +Bulldozer AMD CPUs appear to be missing it. This creates a mismatch +between when the __haswell__ macro gets declared in qsimd_p.h and the +runtime check using the CpuArchHaswell value. That in turn creates a +condition where qInitDrawhelperFunctions() in qdrawhelper.cpp leaves the +memfill pointers set to null. + +#elif defined(__SSE2__) +# ifndef __haswell__ + qt_memfill32 = qt_memfill32_sse2; + qt_memfill64 = qt_memfill64_sse2; +# endif +... +#if defined(QT_COMPILER_SUPPORTS_AVX2) + if (qCpuHasFeature(ArchHaswell)) { + qt_memfill32 = qt_memfill32_avx2; + qt_memfill64 = qt_memfill64_avx2; + +It does this so the qt_memfillXX_sse2 functions don't have to be defined +anywhere, so the QtGui build won't carry unnecessary dead code. + +This is old code (from Qt 4.x) and several improvements I've made for +QtCore are not applied yet. My work for qSimdDispatcher[1] isn't +complete: it might have avoided this problem here, but it would also +have required major work for the draw helpers to work in the first +place. + +[1] https://codereview.qt-project.org/c/qt/qtbase/+/537384 + +Pick-to: 6.8 6.7 6.5 6.2 +Fixes: QTBUG-129193 +Change-Id: Ia427a9e502b0fb46b2bdfffda8e2131b7091c9e9 +Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io> +--- a/src/corelib/global/qsimd_x86_p.h ++++ b/src/corelib/global/qsimd_x86_p.h +@@ -85,16 +85,14 @@ + #define cpu_snb (cpu_wsm \ + | cpu_feature_avx) + #define cpu_ivb (cpu_snb \ +- | cpu_feature_f16c \ +- | cpu_feature_rdrnd) ++ | cpu_feature_f16c) + #define cpu_hsw (cpu_ivb \ + | cpu_feature_avx2 \ + | cpu_feature_fma \ + | cpu_feature_bmi \ + | cpu_feature_bmi2 \ + | cpu_feature_movbe) +-#define cpu_bdw (cpu_hsw \ +- | cpu_feature_rdseed) ++#define cpu_bdw (cpu_hsw) + #define cpu_bdx (cpu_bdw) + #define cpu_skl (cpu_bdw) + #define cpu_skx (cpu_skl \ +@@ -237,9 +235,9 @@ + #define QT_FUNCTION_TARGET_STRING_ARCH_NHM QT_FUNCTION_TARGET_STRING_ARCH_CORE2 ",sse4.1,sse4.2,popcnt" + #define QT_FUNCTION_TARGET_STRING_ARCH_WSM QT_FUNCTION_TARGET_STRING_ARCH_NHM + #define QT_FUNCTION_TARGET_STRING_ARCH_SNB QT_FUNCTION_TARGET_STRING_ARCH_WSM ",avx" +-#define QT_FUNCTION_TARGET_STRING_ARCH_IVB QT_FUNCTION_TARGET_STRING_ARCH_SNB ",f16c,rdrnd,fsgsbase" ++#define QT_FUNCTION_TARGET_STRING_ARCH_IVB QT_FUNCTION_TARGET_STRING_ARCH_SNB ",f16c,fsgsbase" + #define QT_FUNCTION_TARGET_STRING_ARCH_HSW QT_FUNCTION_TARGET_STRING_ARCH_IVB ",avx2,fma,bmi,bmi2,lzcnt,movbe" +-#define QT_FUNCTION_TARGET_STRING_ARCH_BDW QT_FUNCTION_TARGET_STRING_ARCH_HSW ",adx,rdseed" ++#define QT_FUNCTION_TARGET_STRING_ARCH_BDW QT_FUNCTION_TARGET_STRING_ARCH_HSW ",adx" + #define QT_FUNCTION_TARGET_STRING_ARCH_BDX QT_FUNCTION_TARGET_STRING_ARCH_BDW + #define QT_FUNCTION_TARGET_STRING_ARCH_SKL QT_FUNCTION_TARGET_STRING_ARCH_BDW ",xsavec,xsaves" + #define QT_FUNCTION_TARGET_STRING_ARCH_SKX QT_FUNCTION_TARGET_STRING_ARCH_SKL ",avx512f,avx512dq,avx512cd,avx512bw,avx512vl" +@@ -473,9 +471,9 @@ + CpuArchNHM = cpu_nhm, + CpuArchWSM = cpu_wsm, + CpuArchSNB = cpu_snb, +- CpuArchIVB = cpu_ivb, ++ CpuArchIVB = cpu_ivb, ///< rdrnd + CpuArchHSW = cpu_hsw, ///< hle,rtm +- CpuArchBDW = cpu_bdw, ++ CpuArchBDW = cpu_bdw, ///< rdseed + CpuArchBDX = cpu_bdx, + CpuArchSKL = cpu_skl, + CpuArchSKX = cpu_skx, ///< clwb +--- a/util/x86simdgen/3rdparty/simd-intel.conf ++++ b/util/x86simdgen/3rdparty/simd-intel.conf +@@ -142,9 +142,9 @@ + arch=NHM Core2 sse4.1,sse4.2,popcnt + arch=WSM NHM + arch=SNB WSM avx +-arch=IVB SNB f16c,rdrnd,fsgsbase ++arch=IVB SNB f16c,fsgsbase # rdrnd + arch=HSW IVB avx2,fma,bmi,bmi2,lzcnt,movbe # hle,rtm +-arch=BDW HSW adx,rdseed ++arch=BDW HSW adx # rdseed + arch=BDX BDW + arch=SKL BDW xsavec,xsaves + arch=SKX SKL avx512f,avx512dq,avx512cd,avx512bw,avx512vl #clwb diff --git a/dev-qt/qtbase/qtbase-6.7.2-r4.ebuild b/dev-qt/qtbase/qtbase-6.7.2-r5.ebuild index e7e909a26a94..e21fc8158f6c 100644 --- a/dev-qt/qtbase/qtbase-6.7.2-r4.ebuild +++ b/dev-qt/qtbase/qtbase-6.7.2-r5.ebuild @@ -150,6 +150,7 @@ PATCHES=( "${FILESDIR}"/${PN}-6.7.2-float16-sse2.patch "${FILESDIR}"/${PN}-6.7.2-qwindowprivate-crash.patch "${FILESDIR}"/${PN}-6.7.2-qcontiguouscache.patch + "${FILESDIR}"/${PN}-6.7.2-haswell-no-rdrnd.patch ) src_prepare() { |