diff options
author | V3n3RiX <venerix@redcorelinux.org> | 2020-11-25 22:39:15 +0000 |
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committer | V3n3RiX <venerix@redcorelinux.org> | 2020-11-25 22:39:15 +0000 |
commit | d934827bf44b7cfcf6711964418148fa60877668 (patch) | |
tree | 0625f358789b5e015e49db139cc1dbc9be00428f /metadata/md5-cache/sci-electronics/iverilog-11.0 | |
parent | 2e34d110f164bf74d55fced27fe0000201b3eec5 (diff) |
gentoo resync : 25.11.2020
Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-11.0')
-rw-r--r-- | metadata/md5-cache/sci-electronics/iverilog-11.0 | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-11.0 b/metadata/md5-cache/sci-electronics/iverilog-11.0 new file mode 100644 index 000000000000..b2393c591a3d --- /dev/null +++ b/metadata/md5-cache/sci-electronics/iverilog-11.0 @@ -0,0 +1,13 @@ +BDEPEND=dev-util/gperf sys-devel/bison sys-devel/flex >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.1:1.16 >=sys-devel/automake-1.15.1:1.15 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4 +DEFINED_PHASES=install prepare +DEPEND=sys-libs/readline:= sys-libs/zlib +DESCRIPTION=A Verilog simulation and synthesis tool +EAPI=7 +HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog +KEYWORDS=~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86 +LICENSE=LGPL-2.1 +RDEPEND=sys-libs/readline:= sys-libs/zlib +SLOT=0 +SRC_URI=https://github.com/steveicarus/iverilog/archive/v11_0.tar.gz -> iverilog-11.0.tar.gz +_eclasses_=autotools 7d999b62b8749fad43fff00620cedf47 libtool f143db5a74ccd9ca28c1234deffede96 multilib d410501a125f99ffb560b0c523cd3d1e toolchain-funcs 605c126bed8d87e4378d5ff1645330cb +_md5_=53fe7f5f4565527a26b28a22c2a45c7c |