diff options
| author | V3n3RiX <venerix@koprulu.sector> | 2024-01-08 18:59:30 +0000 |
|---|---|---|
| committer | V3n3RiX <venerix@koprulu.sector> | 2024-01-08 18:59:30 +0000 |
| commit | 1e1e7636b59380beebd325e8d256875e4f824230 (patch) | |
| tree | cac3706b236cea47f66f8d45afc943890cd4375e /metadata/md5-cache/sci-electronics/iverilog-11.0 | |
| parent | 5cbf14acf23c82626389931f64cfe3ef12a1c29f (diff) | |
gentoo auto-resync : 08:01:2024 - 18:59:30
Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-11.0')
| -rw-r--r-- | metadata/md5-cache/sci-electronics/iverilog-11.0 | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-11.0 b/metadata/md5-cache/sci-electronics/iverilog-11.0 index 21027c32491c..bcb34e8c3635 100644 --- a/metadata/md5-cache/sci-electronics/iverilog-11.0 +++ b/metadata/md5-cache/sci-electronics/iverilog-11.0 @@ -1,4 +1,4 @@ -BDEPEND=dev-util/gperf sys-devel/bison app-alternatives/lex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.5:1.16 ) || ( >=sys-devel/autoconf-2.72-r1:2.72 >=sys-devel/autoconf-2.71-r6:2.71 ) >=sys-devel/libtool-2.4.7 +BDEPEND=dev-util/gperf app-alternatives/yacc app-alternatives/lex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.5:1.16 ) || ( >=sys-devel/autoconf-2.72-r1:2.72 >=sys-devel/autoconf-2.71-r6:2.71 ) >=sys-devel/libtool-2.4.7 DEFINED_PHASES=install prepare DEPEND=sys-libs/readline:= sys-libs/zlib DESCRIPTION=A Verilog simulation and synthesis tool @@ -11,4 +11,4 @@ RDEPEND=sys-libs/readline:= sys-libs/zlib SLOT=0 SRC_URI=https://github.com/steveicarus/iverilog/archive/v11_0.tar.gz -> iverilog-11.0.tar.gz _eclasses_=autotools 5f729b9cb10d5eda573cd604c93c6dc5 gnuconfig b6b3e92f8b8c996400074b5f61a59256 libtool 9d3a9a889a6fa62ae794f817c156491b multilib c19072c3cd7ac5cb21de013f7e9832e0 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 -_md5_=319f2f7ac50417a0132f534fadccb3c4 +_md5_=0534d8af091e58e6f998b5e34700e039 |