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author | V3n3RiX <venerix@redcorelinux.org> | 2018-07-14 21:18:55 +0100 |
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committer | V3n3RiX <venerix@redcorelinux.org> | 2018-07-14 21:18:55 +0100 |
commit | d4f376e1f7b0d1dcdeda57e248bfbb4c38fbf44a (patch) | |
tree | 2bc7ff142b1713d43d2abb6e1d12842511034e73 /metadata/md5-cache/sci-electronics/iverilog-10.2 | |
parent | dfd4a588d9ed324dfac33806d2e0ff4b5783cc75 (diff) |
gentoo resync : 14.07.2018
Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-10.2')
-rw-r--r-- | metadata/md5-cache/sci-electronics/iverilog-10.2 | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-10.2 b/metadata/md5-cache/sci-electronics/iverilog-10.2 new file mode 100644 index 000000000000..c2ccfae8e7b2 --- /dev/null +++ b/metadata/md5-cache/sci-electronics/iverilog-10.2 @@ -0,0 +1,12 @@ +DEFINED_PHASES=install +DEPEND=app-arch/bzip2 sys-libs/readline:0= sys-libs/zlib:= +DESCRIPTION=A Verilog simulation and synthesis tool +EAPI=6 +HOMEPAGE=http://iverilog.icarus.com/ +IUSE=examples +KEYWORDS=~amd64 ~ppc ~sparc ~x86 +LICENSE=GPL-2 +RDEPEND=app-arch/bzip2 sys-libs/readline:0= sys-libs/zlib:= +SLOT=0 +SRC_URI=ftp://icarus.com/pub/eda/verilog/v10/verilog-10.2.tar.gz +_md5_=9fe4104a245392cdea2cb1101e623711 |