diff options
author | V3n3RiX <venerix@koprulu.sector> | 2024-07-01 08:00:51 +0100 |
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committer | V3n3RiX <venerix@koprulu.sector> | 2024-07-01 08:00:51 +0100 |
commit | d1c14e94a73fba924761cdad7298f3e48c6bc160 (patch) | |
tree | 60b97f0d81b3b06b06acc48ff8856d7c4afa2989 /dev-python/crc32c | |
parent | d5ee59790ee8298b8599b0aa0fa21a98b972a44d (diff) |
gentoo auto-resync : 01:07:2024 - 08:00:50
Diffstat (limited to 'dev-python/crc32c')
-rw-r--r-- | dev-python/crc32c/Manifest | 5 | ||||
-rw-r--r-- | dev-python/crc32c/crc32c-2.4.1.ebuild | 46 | ||||
-rw-r--r-- | dev-python/crc32c/crc32c-2.4.ebuild | 7 | ||||
-rw-r--r-- | dev-python/crc32c/files/crc32c-2.4-sparc.patch | 34 |
4 files changed, 90 insertions, 2 deletions
diff --git a/dev-python/crc32c/Manifest b/dev-python/crc32c/Manifest index 18da5ff96a6d..23da7626c826 100644 --- a/dev-python/crc32c/Manifest +++ b/dev-python/crc32c/Manifest @@ -1,3 +1,6 @@ +AUX crc32c-2.4-sparc.patch 1186 BLAKE2B 7a7d5b0460df87fd22f8f702f87f15bd8b42467e7feeba76b75a7ad8b01b61a933cd4d533df705464b57ce6a3ec9106fb5a04bc7cf3e028a6d3b7dfffd6a14ce SHA512 1aae78ce722c3d4c07ca2f187000e2ef47a96cc02483be4dfa143130dd741e91e220e6680987ca796654d695de61a5c5f151e1fdb825b7dee0c242f98bda0158 +DIST crc32c-2.4.1.tar.gz 38277 BLAKE2B 3d4a0eeb5811e8bc46df30b8890ab409de92dc3cfe2c5c3ab355df3394e56812c19ac26523be2cf9c33bb5825fb6e080b6f27ea77bed5c38d98fbe6c247653fb SHA512 005f95f66e97f552a83b5c94b706224f44280895d70c348fee86943bf1589a94b57eeddde5e18499fea9c77cbcbcfd5691d9d4b33ed788dc885a1333b6db476b DIST crc32c-2.4.tar.gz 38272 BLAKE2B 1273f62794bd646e983737d922c4e1320a4519856b1cedf2d1d1f9b1e47fc767e248b6e00ada48e8f245e47fc18619327e9a8cfa5d88a0569c467ca6147a1974 SHA512 d747dee42184ff025dd6fd7334b65e5caba4066a055943a783b951d09e09339694072ea552aa95579f03a85a7bdb2eb4a8d12dc9a17f0f83d84c0fde534b36cb -EBUILD crc32c-2.4.ebuild 1183 BLAKE2B 694cbcffd132231a15170dd80d5fae6fbc8b7a0cbd703fae43287f4cd27b850cb867d41537a2551e7a2a16d46febbc06ce242a884f16ea15213d1f2bdb1abd8b SHA512 533f2fb152f9ffc484fff12b3fa71d8198f002e0a3e4bd92e82e775f1e034b528d8efe94fc7f2a78c0a7bdf339c4e32a974dc04f332e74167625ce2f8f0906de +EBUILD crc32c-2.4.1.ebuild 1190 BLAKE2B e3bd619bf25c288df490d4c07f53e98a5a6fefe47c7c765558e9ac6f56eddd1f25054e8d41e7f5bf7b878b6c67f2421592f4b798351e86ee54baa93728397b39 SHA512 861a360abf34b9211588d379140ae8fd5259a106efd55f8a567d924e4d220a19ea16e4c019fe90e092afd10f3d0e9ff0ff082a8b1c18bab53eb6ac180ced8785 +EBUILD crc32c-2.4.ebuild 1278 BLAKE2B 394a81948ed8ebff6c163f698f0db4d43d0b42056d6d3b8ac829897221147bb47e10788cb0545355f831a4a0d4957a5bdd5cc6a215955184c42cd9f5f6b4f3c5 SHA512 db8203094c06f573f93d0860ead84d8ec4f49eeb08e116a859ac6e60918a47cdcfc75a91c0afe528d7ad472e444a42f4099383f8b67ce8e2a5be1c57dd6b8540 MISC metadata.xml 340 BLAKE2B 51d7b138caeb04c73b96d68973194bee9c7af76811fa6c886c5aa80415624d00adee76c4187f52bcc740a5f0fafbebd2b9207c5dac3ab191799598c2d5aa275d SHA512 b6c86d6aacc37c0c1fac0382407b9d8821a939e322281192254d95d1b066088268730f1ad7031b3ce9e9aa324db412a0a8ed060ab75d23155e2e682c6d80a93c diff --git a/dev-python/crc32c/crc32c-2.4.1.ebuild b/dev-python/crc32c/crc32c-2.4.1.ebuild new file mode 100644 index 000000000000..73c73f15b871 --- /dev/null +++ b/dev-python/crc32c/crc32c-2.4.1.ebuild @@ -0,0 +1,46 @@ +# Copyright 2024 Gentoo Authors +# Distributed under the terms of the GNU General Public License v2 + +EAPI=8 + +DISTUTILS_EXT=1 +DISTUTILS_USE_PEP517=setuptools +PYTHON_COMPAT=( pypy3 python3_{10..13} ) + +inherit distutils-r1 pypi + +DESCRIPTION="CRC32c algorithm in hardware and software" +HOMEPAGE=" + https://github.com/ICRAR/crc32c/ + https://pypi.org/project/crc32c/ +" + +LICENSE="LGPL-2.1+" +SLOT="0" +KEYWORDS="~amd64 ~arm ~arm64 ~riscv ~sparc ~x86" +# NB: these don't affect the build, they are only used for tests +IUSE="cpu_flags_arm_crc32 cpu_flags_x86_sse4_2" + +distutils_enable_tests pytest + +python_test() { + local -x PYTEST_DISABLE_PLUGIN_AUTOLOAD=1 + local -x CRC32C_SW_MODE + + # force = run "software" code (i.e. unoptimized) + # none = run "hardware" code (i.e. SSE4.2 / ARMv8 CRC32) + for CRC32C_SW_MODE in none force; do + if [[ ${CRC32C_SW_MODE} == none ]]; then + if ! use cpu_flags_arm_crc32 && ! use cpu_flags_x86_sse4_2; then + continue + fi + + # the test suite just skips all tests, so double-check + "${EPYTHON}" -c "import crc32c" || + die "Importing crc32c failed (accelerated code path broken?)" + fi + + einfo "Testing with CRC32C_SW_MODE=${CRC32C_SW_MODE}" + epytest + done +} diff --git a/dev-python/crc32c/crc32c-2.4.ebuild b/dev-python/crc32c/crc32c-2.4.ebuild index 6e0a4600dea6..2444827a45f7 100644 --- a/dev-python/crc32c/crc32c-2.4.ebuild +++ b/dev-python/crc32c/crc32c-2.4.ebuild @@ -17,12 +17,17 @@ HOMEPAGE=" LICENSE="LGPL-2.1+" SLOT="0" -KEYWORDS="~amd64 ~arm ~arm64 ~riscv ~x86" +KEYWORDS="~amd64 ~arm ~arm64 ~riscv ~sparc ~x86" # NB: these don't affect the build, they are only used for tests IUSE="cpu_flags_arm_crc32 cpu_flags_x86_sse4_2" distutils_enable_tests pytest +PATCHES=( + # https://github.com/ICRAR/crc32c/pull/44 + "${FILESDIR}/${P}-sparc.patch" +) + python_test() { local -x PYTEST_DISABLE_PLUGIN_AUTOLOAD=1 local -x CRC32C_SW_MODE diff --git a/dev-python/crc32c/files/crc32c-2.4-sparc.patch b/dev-python/crc32c/files/crc32c-2.4-sparc.patch new file mode 100644 index 000000000000..f2e96638d51b --- /dev/null +++ b/dev-python/crc32c/files/crc32c-2.4-sparc.patch @@ -0,0 +1,34 @@ +From 9d94ecbfe2363c7adf49bddbf31871764faf4f41 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Micha=C5=82=20G=C3=B3rny?= <mgorny@gentoo.org> +Date: Sun, 30 Jun 2024 16:00:34 +0200 +Subject: [PATCH] Fix char signedness issue in _crc32c_sw_slicing_by_8() + +Fix `_crc32c_sw_slicing_by_8()` to use `unsigned char` for `p_buf`, +to fix incorrect results on platforms with signed `char` such as SPARC. +The code has been casting `unsigned char *` to `char *` for no apparent +reason, and this broke the bitshifts in the big endian blocks. + +Particularly, + + crc ^= *(p_buf++) << 16 + +would be XOR-ed against `0xffee0000` rather than `0x00ee0000`. + +Fixes #43 +--- + crc32c_sw.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/crc32c_sw.c b/crc32c_sw.c +index 8382749..67409c9 100644 +--- a/crc32c_sw.c ++++ b/crc32c_sw.c +@@ -490,7 +490,7 @@ const uint32_t crc_tableil8_o88[256] = + + uint32_t _crc32c_sw_slicing_by_8(uint32_t crc, unsigned const char* data, unsigned long length) + { +- const char* p_buf = (const char*) data; ++ unsigned const char* p_buf = data; + size_t initial_bytes = (sizeof(uint32_t) - (intptr_t)p_buf) & (sizeof(uint32_t) - 1); + size_t li; + size_t running_length; |