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Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-10.3')
-rw-r--r--metadata/md5-cache/sci-electronics/iverilog-10.34
1 files changed, 2 insertions, 2 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-10.3 b/metadata/md5-cache/sci-electronics/iverilog-10.3
index a1909c76d609..1873d90e3deb 100644
--- a/metadata/md5-cache/sci-electronics/iverilog-10.3
+++ b/metadata/md5-cache/sci-electronics/iverilog-10.3
@@ -1,4 +1,4 @@
-BDEPEND=dev-util/gperf app-alternatives/yacc app-alternatives/lex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7
+BDEPEND=dev-util/gperf app-alternatives/yacc app-alternatives/lex sys-devel/gnuconfig >=app-portage/elt-patches-20240116 || ( >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3
DEFINED_PHASES=install prepare
DEPEND=sys-libs/readline:= sys-libs/zlib
DESCRIPTION=A Verilog simulation and synthesis tool
@@ -11,5 +11,5 @@ LICENSE=LGPL-2.1
RDEPEND=sys-libs/readline:= sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz -> iverilog-10.3.tar.gz
-_eclasses_=autotools e4cf390b19033d5ca443765bc8537b81 gnuconfig b6b3e92f8b8c996400074b5f61a59256 libtool 9d3a9a889a6fa62ae794f817c156491b multilib c19072c3cd7ac5cb21de013f7e9832e0 toolchain-funcs e56c7649b804f051623c8bc1a1c44084
+_eclasses_=autotools 3af8f60c4bdb23e738db506a630898ee gnuconfig b6b3e92f8b8c996400074b5f61a59256 libtool 5f49a16f67f81bdf873e3d1f10b10001 multilib c19072c3cd7ac5cb21de013f7e9832e0 toolchain-funcs e56c7649b804f051623c8bc1a1c44084
_md5_=cb0738721dd2e6964f211e0712bf2d93