reinit the tree, so we can have metadata

4 files changed, 119 insertions, 0 deletions

diff --git a/sci-electronics/iverilog/Manifest b/sci-electronics/iverilog/Manifest
new file mode 100644
index 000000000000..29a7069ef4b0
--- /dev/null
+++ b/sci-electronics/iverilog/Manifest
@@ -0,0 +1,7 @@
+DIST verilog-0.9.6.tar.gz 1219982 SHA256 25304d5d58d6411fcd1ab94992a505215eea5a6bbd9779c2be2d9d19f38cd54a SHA512 63c18f211eb9711547db65b859551063129cf18acb1196eaa88562f194231079fe929a6f7b8fbe2160863c521f02dde079e792f1b0bbe1c2514deafd55d5288c WHIRLPOOL 137e94edde19f591214847bb729368a8158a0275f3a88cbb1637bf05689cf3cf765a3db429e282b321861b536e7b2059b52390ca0da9f8e9530ea124cedd0cc9
+DIST verilog-0.9.7.tar.gz 1238088 SHA256 7a5e72e17bfb4c3a59264d8f3cc4e70a7c49c1307173348fdd44e079388e7454 SHA512 1a81f132c667f5cd33a11156364a366806ef9b6ef59b86f69df852af79cc92db17df8db0bace4e3c14929b0110df0aa7d83f35f664057e715842acf7bd21c1f5 WHIRLPOOL 4cf808b0fff6d8498a2188785dc8a3befd0272da1e90a02cd767c700074a002de8262c1873e4f16523f527bbb871d50f049d552bb142b2ae7471282c26bc57d0
+EBUILD iverilog-0.9.6.ebuild 1123 SHA256 88eb3aeef72e2c882f38c0194043a9b35dc2341de15d613eed3a3e3394cd5b56 SHA512 b5bfe49d06522810054db72693e30220ceda8e0e1886a45a2094024b6e114cb3c8e943c333308fd0f17facdaa5bf7066aedc33120bed3fbb942ff0320733695a WHIRLPOOL d75ce46a0e33f8d3b96e0006f86d45810e2a933368ce5c3e30e7fa94c026b847e32df11d79a77f51cf0dcc60eb8bbe9c7513931aee50c3d4a24ae13ef74364f5
+EBUILD iverilog-0.9.7.ebuild 1127 SHA256 9f471bc9ee4975fd66cec51acc69495c6822e9b6faae3799ada03c544c8fa994 SHA512 0166372b9aec56da2edce510783bdd9aece5610f418d0ceea081a72f0b7277b62133fcd866360fea449395a7e9bd6a7f24ae03c2373184bd14c1c951e81d4e33 WHIRLPOOL 1b15c183162454e44d40fef8f5bc7ca5b7efe35590bb2968c20c809860803014bbc1a7ba8b4f5f44953b9788b29476aacb82836c109f20f2e25543c88e9f749d
+MISC ChangeLog 2528 SHA256 f6d834fee5ce4f79754ded3b6b2fede2eb5cf0b3db2362f8f607cf83cd1c0ee5 SHA512 86a9556e3d8625b4fa61f4118cd32bad4103ac2eb85fb42cbbb3d7a3afce76788061e01ebb56c0deb87317eda4351dbc6048fb8d0b7797c311ffa26566361e30 WHIRLPOOL bbff18e85b58a5474eca4f4f73f49739418d37e1e2e2fb8135b4ffa44585f1f0358ebd8ea2507dcb98d203c8fa13ec655136c79701e31a017c138b4749ff5ae9
+MISC ChangeLog-2015 7565 SHA256 9efd3a990a5222d012ecbfca65c06ef4ccd0ffa525016ff928995199854560f2 SHA512 c3be5089091f178a6ebd2b274dce5df173b4f1e400113b72d539efff965820c51eee9f16519006dd7821c965c1157210c7e4e91c27dd0ec2303e521085dbf8b3 WHIRLPOOL fac546e6de9a2a3a1987e4b159c3ad1120f815b7dbd5d69dfbca592187a7c1b938b60b2a9f9890e4b554e4132648462693ced296f553d4eb5669fb3d0ba4bc0d
+MISC metadata.xml 611 SHA256 2f37afbc3806d2d7c23ecc4a0e8b2e41a806ffc335a4fa16f3f1f0d073388839 SHA512 83a276b3b5dcb6dff9a03fe2886ad4476833e4a375af2e5c1b1a597a6a16374f843e319bf03283aabe2c7e12e4d5fa0a6125963177c6227e83bdc8dbae7cbd0a WHIRLPOOL e1f43cc0b4ceb18653e3eb94524217be23cee3b54c164ffdc1200b03be2b0fcbf5dd29bf6149ddb5b85ce1b065589a540d04c7d20a2a9f4fa63d9f88ef940f6f
diff --git a/sci-electronics/iverilog/iverilog-0.9.6.ebuild b/sci-electronics/iverilog/iverilog-0.9.6.ebuild
new file mode 100644
index 000000000000..eb137e4aeb13
--- /dev/null
+++ b/sci-electronics/iverilog/iverilog-0.9.6.ebuild
@@ -0,0 +1,49 @@
+# Copyright 1999-2014 Gentoo Foundation
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=4
+
+inherit eutils multilib
+
+DESCRIPTION="A Verilog simulation and synthesis tool"
+SRC_URI="ftp://icarus.com/pub/eda/verilog/v${PV:0:3}/verilog-${PV}.tar.gz"
+HOMEPAGE="http://iverilog.icarus.com/"
+
+LICENSE="GPL-2"
+SLOT="0"
+KEYWORDS="amd64 ppc sparc x86"
+IUSE="examples"
+
+RDEPEND="app-arch/bzip2
+	sys-libs/readline
+	sys-libs/zlib"
+DEPEND="${RDEPEND}"
+
+S="${WORKDIR}/verilog-${PV}"
+
+src_prepare() {
+	# Fix tests
+	mkdir -p lib/ivl
+	touch lib/ivl/ivl
+	sed -i -e 's/driver\/iverilog -B./IVERILOG_ROOT="." driver\/iverilog -B./' Makefile.in || die
+
+	# Fix LDFLAGS
+	sed -i -e 's/@shared@/@shared@ $(LDFLAGS)/' {cadpli,tgt-vhdl,tgt-null,tgt-stub,tgt-vvp}/Makefile.in || die
+}
+
+src_install() {
+	emake -j1 \
+		prefix="${ED}"/usr \
+		mandir="${ED}"/usr/share/man \
+		infodir="${ED}"/usr/share/info \
+		libdir="${ED}"/usr/$(get_libdir) \
+		libdir64="${ED}"/usr/$(get_libdir) \
+		vpidir="${ED}"/usr/$(get_libdir)/ivl \
+		install
+
+	dodoc *.txt
+	if use examples ; then
+		insinto /usr/share/doc/${PF}
+		doins -r examples
+	fi
+}
diff --git a/sci-electronics/iverilog/iverilog-0.9.7.ebuild b/sci-electronics/iverilog/iverilog-0.9.7.ebuild
new file mode 100644
index 000000000000..6a0aa268dd65
--- /dev/null
+++ b/sci-electronics/iverilog/iverilog-0.9.7.ebuild
@@ -0,0 +1,49 @@
+# Copyright 1999-2014 Gentoo Foundation
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=4
+
+inherit eutils multilib
+
+DESCRIPTION="A Verilog simulation and synthesis tool"
+SRC_URI="ftp://icarus.com/pub/eda/verilog/v${PV:0:3}/verilog-${PV}.tar.gz"
+HOMEPAGE="http://iverilog.icarus.com/"
+
+LICENSE="GPL-2"
+SLOT="0"
+KEYWORDS="~amd64 ~ppc ~sparc ~x86"
+IUSE="examples"
+
+RDEPEND="app-arch/bzip2
+	sys-libs/readline
+	sys-libs/zlib"
+DEPEND="${RDEPEND}"
+
+S="${WORKDIR}/verilog-${PV}"
+
+src_prepare() {
+	# Fix tests
+	mkdir -p lib/ivl
+	touch lib/ivl/ivl
+	sed -i -e 's/driver\/iverilog -B./IVERILOG_ROOT="." driver\/iverilog -B./' Makefile.in || die
+
+	# Fix LDFLAGS
+	sed -i -e 's/@shared@/@shared@ $(LDFLAGS)/' {cadpli,tgt-vhdl,tgt-null,tgt-stub,tgt-vvp}/Makefile.in || die
+}
+
+src_install() {
+	emake -j1 \
+		prefix="${ED}"/usr \
+		mandir="${ED}"/usr/share/man \
+		infodir="${ED}"/usr/share/info \
+		libdir="${ED}"/usr/$(get_libdir) \
+		libdir64="${ED}"/usr/$(get_libdir) \
+		vpidir="${ED}"/usr/$(get_libdir)/ivl \
+		install
+
+	dodoc *.txt
+	if use examples ; then
+		insinto /usr/share/doc/${PF}
+		doins -r examples
+	fi
+}
diff --git a/sci-electronics/iverilog/metadata.xml b/sci-electronics/iverilog/metadata.xml
new file mode 100644
index 000000000000..21d969b3bbd1
--- /dev/null
+++ b/sci-electronics/iverilog/metadata.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd">
+<pkgmetadata>
+  <maintainer type="project">
+    <email>sci-electronics@gentoo.org</email>
+    <name>Gentoo Electronics Project</name>
+  </maintainer>
+  <longdescription>
+  Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a
+  compiler, compiling source code writen in Verilog (IEEE-1364) into some target
+  format. The compiler proper is intended to parse and elaborate design
+  descriptions written to the IEEE standard IEEE Std 1364-2001.
+  </longdescription>
+</pkgmetadata>