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authorV3n3RiX <venerix@redcorelinux.org>2017-11-26 11:42:28 +0000
committerV3n3RiX <venerix@redcorelinux.org>2017-11-26 11:42:28 +0000
commit89c6c06b8c42107dd231687a1012354e7d3039fc (patch)
treedad94f4da8a6694f3cb99f7048be2f9cf5f78f97 /sci-electronics/balsa/metadata.xml
parent796cae72cf9ed18ba01256ac1f83a686a2a76036 (diff)
gentoo resync : 26.11.2017
Diffstat (limited to 'sci-electronics/balsa/metadata.xml')
-rw-r--r--sci-electronics/balsa/metadata.xml14
1 files changed, 7 insertions, 7 deletions
diff --git a/sci-electronics/balsa/metadata.xml b/sci-electronics/balsa/metadata.xml
index d547549944cb..8b31894ded35 100644
--- a/sci-electronics/balsa/metadata.xml
+++ b/sci-electronics/balsa/metadata.xml
@@ -6,11 +6,11 @@
<name>Gentoo Electronics Project</name>
</maintainer>
<longdescription>
- Balsa is an asynchronous circuit synthesis system developed over a number of
- years at the APT group of the School Of Computer Science, The University of
- Manchester. Balsa is built around the Handshake Circuits methology and can
- generate gate level netlists from high-level descriptions in the Balsa
- language. Both dual-rail (QDI) and single-rail (bundled data) circuits can be
- generated.
- </longdescription>
+ Balsa is an asynchronous circuit synthesis system developed over a number of
+ years at the APT group of the School Of Computer Science, The University of
+ Manchester. Balsa is built around the Handshake Circuits methology and can
+ generate gate level netlists from high-level descriptions in the Balsa
+ language. Both dual-rail (QDI) and single-rail (bundled data) circuits can be
+ generated.
+ </longdescription>
</pkgmetadata>