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authorV3n3RiX <venerix@redcorelinux.org>2020-01-15 15:51:32 +0000
committerV3n3RiX <venerix@redcorelinux.org>2020-01-15 15:51:32 +0000
commit21435953e16cda318a82334ddbadb3b5c36d9ea7 (patch)
treee1810a4b135afce04b34862ef0fab2bfaeb8aeca /metadata/md5-cache/sci-electronics/iverilog-9999
parent7bc9c63c9da678a7e6fceb095d56c634afd22c56 (diff)
gentoo resync : 15.01.2020
Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-9999')
-rw-r--r--metadata/md5-cache/sci-electronics/iverilog-999913
1 files changed, 13 insertions, 0 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-9999 b/metadata/md5-cache/sci-electronics/iverilog-9999
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--- /dev/null
+++ b/metadata/md5-cache/sci-electronics/iverilog-9999
@@ -0,0 +1,13 @@
+BDEPEND=>=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.1:1.16 >=sys-devel/automake-1.15.1:1.15 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4 >=dev-vcs/git-1.8.2.1[curl]
+DEFINED_PHASES=install prepare unpack
+DEPEND=dev-util/gperf sys-libs/readline:0 sys-libs/zlib
+DESCRIPTION=A Verilog simulation and synthesis tool
+EAPI=7
+HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog
+IUSE=examples
+LICENSE=LGPL-2.1
+PROPERTIES=live
+RDEPEND=sys-libs/readline:0 sys-libs/zlib
+SLOT=0
+_eclasses_=autotools ea7865c8fba1ea8d3639f355fffe1a3c git-r3 809e27702c573cbba31c08ed00bbad33 libtool f143db5a74ccd9ca28c1234deffede96 multilib 1d91b03d42ab6308b5f4f6b598ed110e toolchain-funcs 512eb3367f507ebaa1d1d43ab7d66e6c
+_md5_=4611de40096aeefee1484ed1e55c1b3b