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authorV3n3RiX <venerix@redcorelinux.org>2020-02-29 18:01:47 +0000
committerV3n3RiX <venerix@redcorelinux.org>2020-02-29 18:01:47 +0000
commitceeeb463cc1eef97fd62eaee8bf2196ba04bc384 (patch)
tree9f47ee47c31a0f13f9496879cd88a1042550aa81 /metadata/md5-cache/sci-electronics/iverilog-10.3
parent53cba99042fa967e2a93da9f8db806fe2d035543 (diff)
gentoo (leap year) resync : 29.02.2020
Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-10.3')
-rw-r--r--metadata/md5-cache/sci-electronics/iverilog-10.34
1 files changed, 2 insertions, 2 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-10.3 b/metadata/md5-cache/sci-electronics/iverilog-10.3
index 8e3f99278840..31593f2ad941 100644
--- a/metadata/md5-cache/sci-electronics/iverilog-10.3
+++ b/metadata/md5-cache/sci-electronics/iverilog-10.3
@@ -1,6 +1,6 @@
BDEPEND=>=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.1:1.16 >=sys-devel/automake-1.15.1:1.15 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4
DEFINED_PHASES=install prepare
-DEPEND=dev-util/gperf sys-libs/readline:0 sys-libs/zlib
+DEPEND=dev-util/gperf sys-devel/bison sys-devel/flex sys-libs/readline:0 sys-libs/zlib
DESCRIPTION=A Verilog simulation and synthesis tool
EAPI=7
HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog
@@ -11,4 +11,4 @@ RDEPEND=sys-libs/readline:0 sys-libs/zlib
SLOT=0
SRC_URI=https://github.com/steveicarus/iverilog/archive/v10_3.tar.gz -> iverilog-10.3.tar.gz
_eclasses_=autotools ea7865c8fba1ea8d3639f355fffe1a3c libtool f143db5a74ccd9ca28c1234deffede96 multilib 1d91b03d42ab6308b5f4f6b598ed110e toolchain-funcs 512eb3367f507ebaa1d1d43ab7d66e6c
-_md5_=666ddafe8eee257788ac2452d15720a3
+_md5_=34c57ecfcb7b6f2654c3f36ef2bd8dec