gentoo auto-resync : 14:07:2024 - 12:27:13

10 files changed, 422 insertions, 2 deletions

diff --git a/dev-cpp/Manifest.gz b/dev-cpp/Manifest.gz
index 6fea24e3c52d..28eca7f92a99 100644
--- a/dev-cpp/Manifest.gz
+++ b/dev-cpp/Manifest.gz
diff --git a/dev-cpp/abseil-cpp/Manifest b/dev-cpp/abseil-cpp/Manifest
index 87e4a01b9ad0..d269d37a6827 100644
--- a/dev-cpp/abseil-cpp/Manifest
+++ b/dev-cpp/abseil-cpp/Manifest
@@ -3,6 +3,7 @@ AUX abseil-cpp-20211102.0-r2-cuda11.6-compile-fix.patch 741 BLAKE2B 22bc89e5b0ed
 AUX abseil-cpp-20211102.0-r2-gcc-13.patch 951 BLAKE2B ad2a13d2260d7cfdfe95b07f1582bbf5ce627d8d8bf1e32b70834611065359b95d17b198c2b0aef70ff353dc289903c70ee9be95d40ef38f75c1872f08987eb1 SHA512 73aae8c3c90d87da47a8a37b68721fa06f44abcf02e829fecdcc076999f420a513005e946662bfeb073cf19a06916b1b400b3f35811ddfbe9b0fde75b4d87a53
 AUX abseil-cpp-20211102.0-r2-loong.patch 739 BLAKE2B a3082b6da75719f57287dfac5b67e70ced0ebdbf3e2682c273d7022b024a92fedc8d33c781bafe167675a6a1cd592dbaf915c4031e6dca6aca2513451717cdc8 SHA512 d77e896e145e71b96be32779adb12cbaeabb3a69e5e57a0f47fdf428baf3b6ea22484e9a02979bf15f839417b13e74d0629a6d7207ad0bfa4f44eb9e1eb82867
 AUX abseil-cpp-20230125.2-musl-1.2.4.patch 2203 BLAKE2B 74ebf85e5f35de255fbf5a757655fedd8f5821558ecf700fcc06e30950ce4bb802ca2431cf8b15d05ddc3a7bf2818eec49bf38c2e33d033df0c2973983340ed4 SHA512 404a3c25135573292cbe90f3fb459172a936abc2ec4739e57b8a1dac300a3e0b848ba18aaab5f6dfd12315de736175b962174022a7969149221bf595738bebb1
+AUX abseil-cpp-20230802.0-conditional-use-of-lzcnt.patch 2148 BLAKE2B 978304f3ff8f46ac8fcd7c708f464cacf657f5f4f76a5bab5c4db6e14dcde0bbc7b2ae03c8b74a527218eab737cbacb9219b1a87ee2af8dde8795d3c1b43c7af SHA512 c94ba837440e2c49f3703492f0eb51c7f1930d8d700660d6db56985ad05fe61d3c97656ba8e0a818b843f04c939bdeb4134005420ad561068c52f64ee481f091
 AUX abseil-cpp-20230802.0-sdata-tests.patch 1541 BLAKE2B ae6cebeefc794e89101bd4d0a3a1c022e651dfdb312401fbbf035f6c2afbde8162c132f692e89a075cb1811ae9e0708652c469107047cba49618c0ef752eb108 SHA512 bda7cec902c1f71173b4e7bf2e35c3fffc5de216dc84680e9a0de56b1bb5b9ea4f50cb603e690275e1fc9e2fcbc8ad998a8dadb655fb96d28a651ac80bc2f764
 AUX abseil-cpp-random-tests.patch 660 BLAKE2B 60ef86170310b6ababed9f07fc2e40ca12b278f2202de3d1ae3f028eb081b3de0ba6e245211457e0c2d764142916c2a3c7a46c813ba2bc5536c50edebaf4c3f6 SHA512 d2356539fb38a16cc52cd11106d87613c46a4757827bdea22f4a42f5ea7d557387477ce17a20fa54051488f66b1e628be9e539948cdb1e87970174d3894b1d80
 DIST abseil-cpp-20211102.0.tar.gz 1884080 BLAKE2B a148f3b7cc9516fbeacc25116032a956bfa3cce61b4294c226e826e1171d24c043ab199757a11fae3fec0bc307b2222773a6b4f4563b289f7565b0ce4f72318a SHA512 fed68aa434c02ec6faa9d1c81f1ad35b60ec024b44957e2e0ac31e6075e385c06a3e1b616afeb4bb7c2413191fd7827d82e1f9f0796b52ed21fb2c41dd9031cf
@@ -18,6 +19,7 @@ EBUILD abseil-cpp-20211102.0-r2.ebuild 1812 BLAKE2B 3e8b5486a5b9817c089cae614e17
 EBUILD abseil-cpp-20220623.1.ebuild 1732 BLAKE2B 8134bcb040be826b4f153afddc4c3aae86fd9d773afbf08b50bba323c0d067fd034c92fde3f9c15f73366e910f3641512e81cefa04bc5a9f2830d06e4b8ac3f5 SHA512 ac7802104eb66d08fdcc5904d1d9644ea1511c1f1d8bda2ba8931af6aa56ce5917d59bbb9e68354b8c4d1c38cba1507cb27420e681e3679c88d3bc9538b0e19e
 EBUILD abseil-cpp-20230125.2.ebuild 1693 BLAKE2B ad84c9a1b9b5983029aa5978f1fefc14700c1ffdfd4edf4a4cf2ff782d25cc339b2354a293c51d8853a6a2e0107ed3f7ea8e32685663ad760fc0245c7a4ac79c SHA512 6fe0f3a491f71fcd954201653fcf329385c738a7e43cb18adf802dc2f10c27ceb7c87e8e5303d20cce07dc1f905a5e094d6979a615b14b4cdb0cce5880b1a467
 EBUILD abseil-cpp-20230125.3-r3.ebuild 1640 BLAKE2B 534ee2c085dfb77471eb34a47491abff5a64aafc6052b3875645ed3e490acd0719855f79bc098bd9107ecc5bce406789804825a88f046d3cb47db83be1a7120d SHA512 55d1a88de4c1474c9b5e03e144a874bf15fb5f9b198a188f267d1290d9f92b7ba47106751d0ba6993b87436c49aa2a744d82edd32ee1235e21f6140c57289245
-EBUILD abseil-cpp-20230802.0-r2.ebuild 1647 BLAKE2B 02b204dc37f8efbe4baf8b43268e191325d37610eb5ece67d6ffcd4d0f249043baa9928024abf17424d0c8c7fd0adc8811e0a493bb26e0a37bafec4a8076cc25 SHA512 1b98fb0c0dde809a22eb459188acc18e99464082592a37a357b132ed9817fd7c8470ae390814174b713630a99c736ca84564fbe0e8650c15d4622c39bf461d8b
-EBUILD abseil-cpp-20240116.2-r2.ebuild 1647 BLAKE2B 02b204dc37f8efbe4baf8b43268e191325d37610eb5ece67d6ffcd4d0f249043baa9928024abf17424d0c8c7fd0adc8811e0a493bb26e0a37bafec4a8076cc25 SHA512 1b98fb0c0dde809a22eb459188acc18e99464082592a37a357b132ed9817fd7c8470ae390814174b713630a99c736ca84564fbe0e8650c15d4622c39bf461d8b
+EBUILD abseil-cpp-20230125.3-r4.ebuild 1713 BLAKE2B 1ab709d5aa35d36cc6cb1f64ec1e6ab370971df0a7468303c6b71185f6ef2f69580ce797909d5927fa77a1daa88028130d6a1de40fc5b512aca8c2bd26c07abb SHA512 fc99dc540a83bd6e95e6847d1dae1d8a883d130bd15090c1894cc3ce065d6fac9d2b4fa68fdf84f607b7407ab983186e73d91ee9909d44d4e37615c25789a9be
+EBUILD abseil-cpp-20230802.0-r3.ebuild 1718 BLAKE2B 1a46df3f2b8631c4cc5da5697494999329b85a0469e64f00ff2103425218086c7317594c2d4ae7e49e91fc1e636b782490825c94a01155d0bc4f72bff6e2a72b SHA512 bdbb13ac0faa4ccf7f7a41579311a65853916e7d533a107a84506dcc5463621ba5cc1ebcd1a41e01da5621c98ac4aaae0803175b0a74a02fc8af547afd8d9cbe
+EBUILD abseil-cpp-20240116.2-r3.ebuild 1718 BLAKE2B 1a46df3f2b8631c4cc5da5697494999329b85a0469e64f00ff2103425218086c7317594c2d4ae7e49e91fc1e636b782490825c94a01155d0bc4f72bff6e2a72b SHA512 bdbb13ac0faa4ccf7f7a41579311a65853916e7d533a107a84506dcc5463621ba5cc1ebcd1a41e01da5621c98ac4aaae0803175b0a74a02fc8af547afd8d9cbe
 MISC metadata.xml 250 BLAKE2B f2e7e5ef7661a51822a5d563f7a835c3606c9bbb9688d599637e0950aa68dbacd67592a8c5306528653dd2b5f7100dc6f5e6ac69c5d7bf9777b12c984b53304c SHA512 99565f4efff02cf80efcaa76ad9247db3c0de6f855f37337579cfcd6e01f72a6e176d5e69ef1a1d338afee6a07c1620273fe56af046a60f195de4d8894a8d7f9
diff --git a/dev-cpp/abseil-cpp/abseil-cpp-20230125.3-r4.ebuild b/dev-cpp/abseil-cpp/abseil-cpp-20230125.3-r4.ebuild
new file mode 100644
index 000000000000..87f1b86c7690
--- /dev/null
+++ b/dev-cpp/abseil-cpp/abseil-cpp-20230125.3-r4.ebuild
@@ -0,0 +1,67 @@
+# Copyright 2020-2024 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=8
+
+PYTHON_COMPAT=( python3_{10..12} )
+
+inherit cmake-multilib python-any-r1
+
+DESCRIPTION="Abseil Common Libraries (C++), LTS Branch"
+HOMEPAGE="https://abseil.io/"
+SRC_URI="https://github.com/abseil/abseil-cpp/archive/${PV}.tar.gz -> ${P}.tar.gz"
+
+LICENSE="Apache-2.0"
+SLOT="0/${PV%%.*}.0"
+KEYWORDS="~amd64 ~arm ~arm64 ~loong ~ppc64 ~riscv ~x86"
+IUSE="test"
+
+RDEPEND=">=dev-cpp/gtest-1.13.0[${MULTILIB_USEDEP}]"
+DEPEND="${RDEPEND}"
+BDEPEND="
+	${PYTHON_DEPS}
+	test? (
+		sys-libs/timezone-data
+	)
+"
+
+RESTRICT="!test? ( test )"
+
+PATCHES=(
+	"${FILESDIR}"/${PN}-20230125.2-musl-1.2.4.patch #906218
+	"${FILESDIR}"/${PN}-random-tests.patch #935417
+	"${FILESDIR}/${PN}-20230802.0-conditional-use-of-lzcnt.patch" #934337
+)
+
+src_prepare() {
+	cmake_src_prepare
+
+	# un-hardcode abseil compiler flags
+	sed -i \
+		-e '/"-maes",/d' \
+		-e '/"-msse4.1",/d' \
+		-e '/"-mfpu=neon"/d' \
+		-e '/"-march=armv8-a+crypto"/d' \
+		absl/copts/copts.py || die
+
+	# now generate cmake files
+	python_fix_shebang absl/copts/generate_copts.py
+	absl/copts/generate_copts.py || die
+}
+
+multilib_src_configure() {
+	local mycmakeargs=(
+		# We use -std=c++14 here so that abseil-cpp's string_view is used
+		# See the discussion in https://github.com/gentoo/gentoo/pull/32281.
+		-DCMAKE_CXX_STANDARD=14
+		-DABSL_ENABLE_INSTALL=TRUE
+		-DABSL_USE_EXTERNAL_GOOGLETEST=ON
+		-DABSL_PROPAGATE_CXX_STD=TRUE
+		# TEST_HELPERS needed for protobuf (bug #915902)
+		-DABSL_BUILD_TEST_HELPERS=ON
+		-DABSL_BUILD_TESTING=$(usex test ON OFF)
+		$(usex test -DBUILD_TESTING=ON '') # intentional usex, it used both variables for tests.
+	)
+
+	cmake_src_configure
+}
diff --git a/dev-cpp/abseil-cpp/abseil-cpp-20230802.0-r2.ebuild b/dev-cpp/abseil-cpp/abseil-cpp-20230802.0-r3.ebuild
index 9a9c217bda00..dc13dfe5045f 100644
--- a/dev-cpp/abseil-cpp/abseil-cpp-20230802.0-r2.ebuild
+++ b/dev-cpp/abseil-cpp/abseil-cpp-20230802.0-r3.ebuild
@@ -30,6 +30,7 @@ RESTRICT="!test? ( test )"
 PATCHES=(
 	"${FILESDIR}/${PN}-20230802.0-sdata-tests.patch"
 	"${FILESDIR}/${PN}-random-tests.patch" #935417
+	"${FILESDIR}/${PN}-20230802.0-conditional-use-of-lzcnt.patch" #934337
 )
 
 src_prepare() {
diff --git a/dev-cpp/abseil-cpp/abseil-cpp-20240116.2-r2.ebuild b/dev-cpp/abseil-cpp/abseil-cpp-20240116.2-r3.ebuild
index 9a9c217bda00..dc13dfe5045f 100644
--- a/dev-cpp/abseil-cpp/abseil-cpp-20240116.2-r2.ebuild
+++ b/dev-cpp/abseil-cpp/abseil-cpp-20240116.2-r3.ebuild
@@ -30,6 +30,7 @@ RESTRICT="!test? ( test )"
 PATCHES=(
 	"${FILESDIR}/${PN}-20230802.0-sdata-tests.patch"
 	"${FILESDIR}/${PN}-random-tests.patch" #935417
+	"${FILESDIR}/${PN}-20230802.0-conditional-use-of-lzcnt.patch" #934337
 )
 
 src_prepare() {
diff --git a/dev-cpp/abseil-cpp/files/abseil-cpp-20230802.0-conditional-use-of-lzcnt.patch b/dev-cpp/abseil-cpp/files/abseil-cpp-20230802.0-conditional-use-of-lzcnt.patch
new file mode 100644
index 000000000000..1fa00d9ff622
--- /dev/null
+++ b/dev-cpp/abseil-cpp/files/abseil-cpp-20230802.0-conditional-use-of-lzcnt.patch
@@ -0,0 +1,49 @@
+Bug: https://bugs.gentoo.org/934337

+From: https://github.com/abseil/abseil-cpp/commit/c1e1b47d989978cde8c5a2a219df425b785a0c47.patch

+From c1e1b47d989978cde8c5a2a219df425b785a0c47 Mon Sep 17 00:00:00 2001

+From: Derek Mauro <dmauro@google.com>

+Date: Fri, 3 May 2024 09:14:22 -0700

+Subject: [PATCH] Use __builtin_ctzg and __builtin_clzg in the implementations

+ of CountTrailingZeroesNonzero16 and CountLeadingZeroes16 when they are

+ available.

+

+GCC 14 and Clang 19 adds these new builtins. The g-suffix is for

+"generic". The s-suffix on __builtin_ctzs and __builtin_clzs is for

+"short". GCC never implemented the short versions and #1664 reports

+GCC 14 (pre-release) gives an error here, although this may be a

+pre-release bug.

+

+Fixes #1664

+

+PiperOrigin-RevId: 630408249

+Change-Id: I4aedcc82b85430f50d025f8eb1cab089c6fcd1bc

+---

+ absl/numeric/internal/bits.h | 8 ++++++--

+ 1 file changed, 6 insertions(+), 2 deletions(-)

+

+diff --git a/absl/numeric/internal/bits.h b/absl/numeric/internal/bits.h

+index bfef06bce1f..0917464d6ad 100644

+--- a/absl/numeric/internal/bits.h

++++ b/absl/numeric/internal/bits.h

+@@ -167,7 +167,9 @@ CountLeadingZeroes32(uint32_t x) {

+ 

+ ABSL_ATTRIBUTE_ALWAYS_INLINE ABSL_INTERNAL_CONSTEXPR_CLZ inline int

+ CountLeadingZeroes16(uint16_t x) {

+-#if ABSL_HAVE_BUILTIN(__builtin_clzs)

++#if ABSL_HAVE_BUILTIN(__builtin_clzg)

++  return x == 0 ? 16 : __builtin_clzg(x);

++#elif ABSL_HAVE_BUILTIN(__builtin_clzs)

+   static_assert(sizeof(unsigned short) == sizeof(x),  // NOLINT(runtime/int)

+                 "__builtin_clzs does not take 16-bit arg");

+   return x == 0 ? 16 : __builtin_clzs(x);

+@@ -303,7 +305,9 @@ CountTrailingZeroesNonzero64(uint64_t x) {

+ 

+ ABSL_ATTRIBUTE_ALWAYS_INLINE ABSL_INTERNAL_CONSTEXPR_CTZ inline int

+ CountTrailingZeroesNonzero16(uint16_t x) {

+-#if ABSL_HAVE_BUILTIN(__builtin_ctzs)

++#if ABSL_HAVE_BUILTIN(__builtin_ctzg)

++  return __builtin_ctzg(x);

++#elif ABSL_HAVE_BUILTIN(__builtin_ctzs)

+   static_assert(sizeof(unsigned short) == sizeof(x),  // NOLINT(runtime/int)

+                 "__builtin_ctzs does not take 16-bit arg");

+   return __builtin_ctzs(x);

diff --git a/dev-cpp/xsimd/Manifest b/dev-cpp/xsimd/Manifest
index 21d48dbecda6..f69c57ee861c 100644
--- a/dev-cpp/xsimd/Manifest
+++ b/dev-cpp/xsimd/Manifest
@@ -1,8 +1,12 @@
 AUX xsimd-11.1.0-c++17.patch 1429 BLAKE2B 23be29fdd74ed37632bd1fba0ffdedf08af48f14985494f5befac4afb34622bb44e294e954d9d4e57a07ee6e9d988a48a93dd1b66a6f6206b79bd7c0cb600cc8 SHA512 41a474a6d768aec39e6760d4ff60017a5e3d5c4349bf244d3de1464bd9b06022d6cadcd4f91cc17a6630f38f1b0fe0e3aa4fa5a6810b8c57d649f5a8da28c217
 AUX xsimd-11.1.0-no-march.patch 3720 BLAKE2B 21adb3c35d8161db849c90363781642fa9c1051686e6dba00e55396adc905d1276540c663d34ab7bd124daa3fe6e367c5c41c17d7e0f31d55b82b1488fbdee0f SHA512 567f535a2a0dcdb02f05b53beba48e9704ef40d63df9531014257e0773a8df09854245ec5d22e6b7cffdf7541e8f48e55e2ea8faa513ca93f952aa177757bb3a
 AUX xsimd-12.1.1-no-march.patch 3739 BLAKE2B 44fb2ddfb55b8109e3b92a1479647ecbaf0f16fe949bc70c2f12fcfbd1cb0d87bfdf43d0fc2ac835bde8dbe843527d6426692a2fd0b504b6cfdcee824ae5d262 SHA512 82d5d1834af23f94ef0421c328e8f0b84c4c3b05acbd3c05bc9ea9c56c4078e827b8dcecf5f726deb35de9b3693c63effd5b7085c07a3b964f25a577d53c6da2
+AUX xsimd-13.0.0-detection-simd-with-mitigations.patch 5810 BLAKE2B a9a2bf8211e60c4e370c6c845cb06a1b17c7666778e907ba3215c9309a82e70efba2462cfb77298f15dd2366b0354c5830c99a3d08cfd619981b5e9c5179726b SHA512 b01b33722aa0a45f74d4df9810ea442ec37932aeb188c5c40e63f15533667b82b0ad5a0c2c737e18ad327e70c44bf13669f46dcc57fcde305dd94f0d24421e9f
+AUX xsimd-13.0.0-sve-rvv.patch 3244 BLAKE2B 50681c648f98caf5efa5c916618be090435f1e35ecc1877e4c933e31d2e869c25cc36b6c8d885ec0749753b07b903125b17dbfd55e95e5f5e1a3e01363942463 SHA512 36f4dfee1103155b1dc9159293690df937fd554d0ce401834193e59283f65beb366f9a48f5fc25bb367a11c0c2b7a57b7e225d1a9cd74de9f1a143e919c0b052
 DIST xsimd-11.1.0.tar.gz 219350 BLAKE2B 2bbbc4f7dbe489a407fe798b146c008aba44664efc943c2e1507d5c6e7da2a03ed91abf0d872e5abf9bd94be3e76bef276ec5b47d4e356b42a7b4c680bd6f3d9 SHA512 3a6141dfa4d95a977f4222880dfd06197613d153a78a84653022423279eec037ea9def08ae225aba7231c0b2c434ab7c907c965f8367fb0db9b96113980b51f3
 DIST xsimd-12.1.1.tar.gz 253141 BLAKE2B 29efbb045d8ade8737d702a73f3d0a912111dd4fbc84485c0e54c8b06d73edbb4b85f4b51e24da9bed0dea010b0cce9d99b57e20e8b94d3daf90d46031548eb9 SHA512 8e45a8e9b28358d5f20f713ea19a8c366edc62790c27984149f283dfe808d78a549c8ec465e8b3677d7e30b2cb80093908de364bbb9dc80683f5fdfb843131e1
+DIST xsimd-13.0.0.tar.gz 259967 BLAKE2B 63267c75a7e8ed2e8689a912e79a1d012ff3cf3813969f97a640801e372ec9e66a6e3d3034b6918a30dc3374e8211fd1107f1309156354b6bca6ba17c6f132b4 SHA512 cdc42ddad3353297cf25ea2b6b3f09967f5f388efc26241f2997979fdbbac072819ff771145bc5bfa86cb326cca84b4119e8e6e3f658407961cf203a40603a7f
 EBUILD xsimd-11.1.0-r1.ebuild 1034 BLAKE2B fdc6a900c039da14a5091ee7ed4a9ea9e2611610a9bd812fc6be91544e08e2f91d101b0800e70c8df224bab2d08677723e9aece300edbca585d9e31ee9425c4a SHA512 0e00b0d9143cd2c2736be80f35616fbb17789bc9696efb9ee340d13243b2c1c299314549faeeb6e02b3029e96709d8e7c108fe2b58cd5658aa60a8e9ff44c1e1
 EBUILD xsimd-12.1.1.ebuild 1045 BLAKE2B 263ebcc57be8996455820190be8d339f4f22ceb17d4da6e8f1438502307b429b091cf721d2ea9e55e7a2a6c66e65d1d824a271af3f5aeec0d66aa519c2e345c7 SHA512 998d903d3841879ce50c7e812b74d04bea52f49eb02222d886d4322f4cd7dd386c6eecf95f39b26668c93d91ac899c2c336ba6a677d3bd354e07c5aff52d8ed3
+EBUILD xsimd-13.0.0.ebuild 1161 BLAKE2B fecc69fcb7fb158a22d5bf98f3b4f0e7ea7a69364daf25371f2fe9979fd0b8b2a6bb1d1fcbbe6dd54d4c5d0cd1877cf2eb9f56d357e98d722ced29136b701732 SHA512 536dcb2b6373a3463142d03cca4544856d529106bd049aca0e720c14a09cf4457a4d9a42de0fe3bbd859b7934cb180469191f513e5013155bc100944702f018e
 MISC metadata.xml 385 BLAKE2B e22c7622c338c277eee7dd048463a2d3244fffcd255b1a9dd9652a1295c3c1f0043e67fab28b084b3f10b03b5fd5e36b4f713c040ddc168ac6be9287af14e031 SHA512 5826eb1e62fa79c1e355668ad83a9e4e113b3cf154535537181597062f952ad436c56c8d9dd9f3599815307e33f4e1366b2a9b109d27c53bc112fe0a4c62d885
diff --git a/dev-cpp/xsimd/files/xsimd-13.0.0-detection-simd-with-mitigations.patch b/dev-cpp/xsimd/files/xsimd-13.0.0-detection-simd-with-mitigations.patch
new file mode 100644
index 000000000000..6aab22cd8416
--- /dev/null
+++ b/dev-cpp/xsimd/files/xsimd-13.0.0-detection-simd-with-mitigations.patch
@@ -0,0 +1,148 @@
+https://mail.kde.org/pipermail/distributions/2024-July/001511.html
+https://github.com/xtensor-stack/xsimd/commit/96edf0340492fa9c080f5182b38358ca85baef5e
+
+From 96edf0340492fa9c080f5182b38358ca85baef5e Mon Sep 17 00:00:00 2001
+From: Dmitry Kazakov <dimula73@gmail.com>
+Date: Tue, 28 May 2024 22:21:08 +0200
+Subject: [PATCH] Fix detection of SSE/AVX/AVX512 when they are explicitly 
+ disabled by OS
+
+Some CPU vulnerability mitigations may disable AVX functionality
+on the hardware level via the XCR0 register. We should check that
+manually to verify that OS actually allows us to use this feature.
+
+See https://bugs.kde.org/show_bug.cgi?id=484622
+
+Fix #1025
+---
+ include/xsimd/config/xsimd_cpuid.hpp | 91 ++++++++++++++++++++++------
+ 1 file changed, 72 insertions(+), 19 deletions(-)
+
+diff --git a/include/xsimd/config/xsimd_cpuid.hpp b/include/xsimd/config/xsimd_cpuid.hpp
+index f22089bac..6dda3be09 100644
+--- a/include/xsimd/config/xsimd_cpuid.hpp
++++ b/include/xsimd/config/xsimd_cpuid.hpp
+@@ -114,6 +114,35 @@ namespace xsimd
+ #endif
+ 
+ #elif defined(__x86_64__) || defined(__i386__) || defined(_M_AMD64) || defined(_M_IX86)
++
++                auto get_xcr0_low = []() noexcept
++                {
++                    uint32_t xcr0;
++
++#if defined(_MSC_VER) && _MSC_VER >= 1400
++
++                    xcr0 = (uint32_t)_xgetbv(0);
++
++#elif defined(__GNUC__)
++
++                    __asm__(
++                        "xorl %%ecx, %%ecx\n"
++                        "xgetbv\n"
++                        : "=a"(xcr0)
++                        :
++#if defined(__i386__)
++                        : "ecx", "edx"
++#else
++                        : "rcx", "rdx"
++#endif
++                    );
++
++#else /* _MSC_VER < 1400 */
++#error "_MSC_VER < 1400 is not supported"
++#endif /* _MSC_VER && _MSC_VER >= 1400 */
++                    return xcr0;
++                };
++
+                 auto get_cpuid = [](int reg[4], int level, int count = 0) noexcept
+                 {
+ 
+@@ -148,19 +177,43 @@ namespace xsimd
+ 
+                 get_cpuid(regs1, 0x1);
+ 
+-                sse2 = regs1[3] >> 26 & 1;
+-                sse3 = regs1[2] >> 0 & 1;
+-                ssse3 = regs1[2] >> 9 & 1;
+-                sse4_1 = regs1[2] >> 19 & 1;
+-                sse4_2 = regs1[2] >> 20 & 1;
+-                fma3_sse42 = regs1[2] >> 12 & 1;
++                // OS can explicitly disable the usage of SSE/AVX extensions
++                // by setting an appropriate flag in CR0 register
++                //
++                // https://docs.kernel.org/admin-guide/hw-vuln/gather_data_sampling.html
++
++                unsigned sse_state_os_enabled = 1;
++                unsigned avx_state_os_enabled = 1;
++                unsigned avx512_state_os_enabled = 1;
++
++                // OSXSAVE: A value of 1 indicates that the OS has set CR4.OSXSAVE[bit
++                // 18] to enable XSETBV/XGETBV instructions to access XCR0 and
++                // to support processor extended state management using
++                // XSAVE/XRSTOR.
++                bool osxsave = regs1[2] >> 27 & 1;
++                if (osxsave)
++                {
++
++                    uint32_t xcr0 = get_xcr0_low();
++
++                    sse_state_os_enabled = xcr0 >> 1 & 1;
++                    avx_state_os_enabled = xcr0 >> 2 & sse_state_os_enabled;
++                    avx512_state_os_enabled = xcr0 >> 6 & avx_state_os_enabled;
++                }
++
++                sse2 = regs1[3] >> 26 & sse_state_os_enabled;
++                sse3 = regs1[2] >> 0 & sse_state_os_enabled;
++                ssse3 = regs1[2] >> 9 & sse_state_os_enabled;
++                sse4_1 = regs1[2] >> 19 & sse_state_os_enabled;
++                sse4_2 = regs1[2] >> 20 & sse_state_os_enabled;
++                fma3_sse42 = regs1[2] >> 12 & sse_state_os_enabled;
+ 
+-                avx = regs1[2] >> 28 & 1;
++                avx = regs1[2] >> 28 & avx_state_os_enabled;
+                 fma3_avx = avx && fma3_sse42;
+ 
+                 int regs8[4];
+                 get_cpuid(regs8, 0x80000001);
+-                fma4 = regs8[2] >> 16 & 1;
++                fma4 = regs8[2] >> 16 & avx_state_os_enabled;
+ 
+                 // sse4a = regs[2] >> 6 & 1;
+ 
+@@ -168,23 +221,23 @@ namespace xsimd
+ 
+                 int regs7[4];
+                 get_cpuid(regs7, 0x7);
+-                avx2 = regs7[1] >> 5 & 1;
++                avx2 = regs7[1] >> 5 & avx_state_os_enabled;
+ 
+                 int regs7a[4];
+                 get_cpuid(regs7a, 0x7, 0x1);
+-                avxvnni = regs7a[0] >> 4 & 1;
++                avxvnni = regs7a[0] >> 4 & avx_state_os_enabled;
+ 
+                 fma3_avx2 = avx2 && fma3_sse42;
+ 
+-                avx512f = regs7[1] >> 16 & 1;
+-                avx512cd = regs7[1] >> 28 & 1;
+-                avx512dq = regs7[1] >> 17 & 1;
+-                avx512bw = regs7[1] >> 30 & 1;
+-                avx512er = regs7[1] >> 27 & 1;
+-                avx512pf = regs7[1] >> 26 & 1;
+-                avx512ifma = regs7[1] >> 21 & 1;
+-                avx512vbmi = regs7[2] >> 1 & 1;
+-                avx512vnni_bw = regs7[2] >> 11 & 1;
++                avx512f = regs7[1] >> 16 & avx512_state_os_enabled;
++                avx512cd = regs7[1] >> 28 & avx512_state_os_enabled;
++                avx512dq = regs7[1] >> 17 & avx512_state_os_enabled;
++                avx512bw = regs7[1] >> 30 & avx512_state_os_enabled;
++                avx512er = regs7[1] >> 27 & avx512_state_os_enabled;
++                avx512pf = regs7[1] >> 26 & avx512_state_os_enabled;
++                avx512ifma = regs7[1] >> 21 & avx512_state_os_enabled;
++                avx512vbmi = regs7[2] >> 1 & avx512_state_os_enabled;
++                avx512vnni_bw = regs7[2] >> 11 & avx512_state_os_enabled;
+                 avx512vnni_vbmi = avx512vbmi && avx512vnni_bw;
+ #endif
+             }
+
diff --git a/dev-cpp/xsimd/files/xsimd-13.0.0-sve-rvv.patch b/dev-cpp/xsimd/files/xsimd-13.0.0-sve-rvv.patch
new file mode 100644
index 000000000000..38ea56d1baa2
--- /dev/null
+++ b/dev-cpp/xsimd/files/xsimd-13.0.0-sve-rvv.patch
@@ -0,0 +1,88 @@
+https://mail.kde.org/pipermail/distributions/2024-July/001511.html
+https://github.com/xtensor-stack/xsimd/commit/80a59235e3ffa51659aaa06f002bfd088b77023c
+
+From 80a59235e3ffa51659aaa06f002bfd088b77023c Mon Sep 17 00:00:00 2001
+From: Dmitry Kazakov <dimula73@gmail.com>
+Date: Fri, 14 Jun 2024 10:19:55 +0200
+Subject: [PATCH] Fix xsimd::available_architectures().has() for sve and rvv
+ archs
+
+Ideally the patch CPU detection code should also check if the length
+of SVE and RVV is actually supported by the current CPU implementation
+(i.e. ZCR_Elx.LEN register for SVE and something else for RVV), but
+I don't have such CPUs/emulators handy, so I cannot add such checks.
+
+Given that xsimd::available_architectures().has() is a new feature
+of XSIMD13 and the length check has never been present in XSIMD, this
+bug is not a regression at least.
+
+The patch also adds a unittest that reproduces the error the patch fixes
+---
+ include/xsimd/config/xsimd_cpuid.hpp | 12 ++++++++++--
+ test/test_arch.cpp                   | 15 +++++++++++++++
+ 2 files changed, 25 insertions(+), 2 deletions(-)
+
+diff --git a/include/xsimd/config/xsimd_cpuid.hpp b/include/xsimd/config/xsimd_cpuid.hpp
+index 6dda3be09..8021fceb8 100644
+--- a/include/xsimd/config/xsimd_cpuid.hpp
++++ b/include/xsimd/config/xsimd_cpuid.hpp
+@@ -42,6 +42,10 @@ namespace xsimd
+ #define ARCH_FIELD_EX(arch, field_name) \
+     unsigned field_name;                \
+     XSIMD_INLINE bool has(::xsimd::arch) const { return this->field_name; }
++
++#define ARCH_FIELD_EX_REUSE(arch, field_name) \
++    XSIMD_INLINE bool has(::xsimd::arch) const { return this->field_name; }
++
+ #define ARCH_FIELD(name) ARCH_FIELD_EX(name, name)
+ 
+             ARCH_FIELD(sse2)
+@@ -72,8 +76,12 @@ namespace xsimd
+             ARCH_FIELD(neon)
+             ARCH_FIELD(neon64)
+             ARCH_FIELD_EX(i8mm<::xsimd::neon64>, i8mm_neon64)
+-            ARCH_FIELD(sve)
+-            ARCH_FIELD(rvv)
++            ARCH_FIELD_EX(detail::sve<512>, sve)
++            ARCH_FIELD_EX_REUSE(detail::sve<256>, sve)
++            ARCH_FIELD_EX_REUSE(detail::sve<128>, sve)
++            ARCH_FIELD_EX(detail::rvv<512>, rvv)
++            ARCH_FIELD_EX_REUSE(detail::rvv<256>, rvv)
++            ARCH_FIELD_EX_REUSE(detail::rvv<128>, rvv)
+             ARCH_FIELD(wasm)
+ 
+ #undef ARCH_FIELD
+diff --git a/test/test_arch.cpp b/test/test_arch.cpp
+index b42073358..f1f50d546 100644
+--- a/test/test_arch.cpp
++++ b/test/test_arch.cpp
+@@ -38,6 +38,16 @@ struct check_supported
+     }
+ };
+ 
++struct check_cpu_has_intruction_set
++{
++    template <class Arch>
++    void operator()(Arch arch) const
++    {
++        static_assert(std::is_same<decltype(xsimd::available_architectures().has(arch)), bool>::value,
++                      "cannot test instruction set availability on CPU");
++    }
++};
++
+ struct check_available
+ {
+     template <class Arch>
+@@ -71,6 +81,11 @@ TEST_CASE("[multi arch support]")
+         xsimd::supported_architectures::for_each(check_supported {});
+     }
+ 
++    SUBCASE("xsimd::available_architectures::has")
++    {
++        xsimd::all_architectures::for_each(check_cpu_has_intruction_set {});
++    }
++
+     SUBCASE("xsimd::default_arch::name")
+     {
+         constexpr char const* name = xsimd::default_arch::name();
+
diff --git a/dev-cpp/xsimd/xsimd-13.0.0.ebuild b/dev-cpp/xsimd/xsimd-13.0.0.ebuild
new file mode 100644
index 000000000000..41414ef626b6
--- /dev/null
+++ b/dev-cpp/xsimd/xsimd-13.0.0.ebuild
@@ -0,0 +1,60 @@
+# Copyright 2023-2024 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI=8
+
+inherit cmake
+
+DESCRIPTION="C++ wrappers for SIMD intrinsics"
+HOMEPAGE="https://github.com/xtensor-stack/xsimd"
+SRC_URI="https://github.com/xtensor-stack/${PN}/archive/refs/tags/${PV}.tar.gz
+	-> ${P}.tar.gz"
+
+LICENSE="BSD"
+SLOT="0"
+KEYWORDS="~amd64 ~arm ~arm64 ~hppa ~loong ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86"
+IUSE="doc test"
+RESTRICT="!test? ( test )"
+
+BDEPEND="
+	doc? (
+		app-text/doxygen
+		dev-python/breathe
+		dev-python/sphinx
+		dev-python/sphinx-rtd-theme
+	)
+	test? ( dev-cpp/doctest )"
+
+PATCHES=(
+	"${FILESDIR}"/${PN}-11.1.0-c++17.patch
+	"${FILESDIR}"/${PN}-12.1.1-no-march.patch
+	"${FILESDIR}"/${PN}-13.0.0-sve-rvv.patch
+	"${FILESDIR}"/${PN}-13.0.0-detection-simd-with-mitigations.patch
+)
+
+src_prepare() {
+	sed -i \
+		-e '/fPIC/d' \
+		test/CMakeLists.txt \
+		|| die
+	cmake_src_prepare
+}
+
+src_configure() {
+	local mycmakeargs=(
+		-DBUILD_TESTS=$(usex test)
+	)
+	cmake_src_configure
+}
+
+src_compile() {
+	cmake_src_compile
+	use doc && emake -C docs html
+}
+
+src_install() {
+	cmake_src_install
+	if use doc; then
+		dodoc -r docs/build/html
+	fi
+}