diff options
author | V3n3RiX <venerix@redcorelinux.org> | 2019-05-18 00:10:51 +0100 |
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committer | V3n3RiX <venerix@redcorelinux.org> | 2019-05-18 00:10:51 +0100 |
commit | eccb70a7f91b2d22582587f26d1a28bb31408b45 (patch) | |
tree | 3223e1fd54201bcf4ebecac6fbe87361cbe643e2 /app-emulation/qemu/files | |
parent | a2810985afabcc31d3eace5e61d8ea25b852ba17 (diff) |
gentoo resync : 18.05.2019
Diffstat (limited to 'app-emulation/qemu/files')
-rw-r--r-- | app-emulation/qemu/files/qemu-3.1.0-md-clear-md-no.patch | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/app-emulation/qemu/files/qemu-3.1.0-md-clear-md-no.patch b/app-emulation/qemu/files/qemu-3.1.0-md-clear-md-no.patch new file mode 100644 index 000000000000..a7b3e8cb8f20 --- /dev/null +++ b/app-emulation/qemu/files/qemu-3.1.0-md-clear-md-no.patch @@ -0,0 +1,61 @@ +From 0fb766134bd97ead71646e13349f93769e536ed9 Mon Sep 17 00:00:00 2001 +From: Matthias Maier <tamiko@43-1.org> +Date: Fri, 17 May 2019 02:21:10 -0500 +Subject: [PATCH] Define md-clear bit, expose md-no CPUID + +Fixes for CVE-2018-121{26|27|30}, CVE-2019-11091 + +See related fixes for Ubuntu: + https://launchpad.net/ubuntu/+source/qemu/1:3.1+dfsg-2ubuntu3.1 +--- + target/i386/cpu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index d6bb57d2..331a364a 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -1076,7 +1076,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { + .feat_names = { + NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", + NULL, NULL, NULL, NULL, +- NULL, NULL, NULL, NULL, ++ NULL, NULL, "md-clear", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +@@ -1183,7 +1183,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { + .type = MSR_FEATURE_WORD, + .feat_names = { + "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", +- "ssb-no", NULL, NULL, NULL, ++ "ssb-no", "mds-no", NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +diff --git a/target/i386/cpu.h b/target/i386/cpu.h +index 83fb5225..d0bab4d7 100644 +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -694,6 +694,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; + + #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ + #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ ++#define CPUID_7_0_EDX_MD_CLEAR (1U << 10) /* Microarchitectural Data Clear */ + #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ + #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ + #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ +diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c +index 4d957fe8..b453552f 100644 +--- a/target/i386/hvf/x86_cpuid.c ++++ b/target/i386/hvf/x86_cpuid.c +@@ -90,7 +90,8 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, + } + + ecx &= CPUID_7_0_ECX_AVX512BMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ; +- edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS; ++ edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS | \ ++ CPUID_7_0_EDX_MD_CLEAR; + } else { + ebx = 0; + ecx = 0; |