From 9ee6d97c2883d42f204a533a8bc1f4562df778fb Mon Sep 17 00:00:00 2001 From: V3n3RiX Date: Wed, 16 Sep 2020 09:32:48 +0100 Subject: gentoo resync : 16.09.2020 --- metadata/md5-cache/sci-electronics/iverilog-9999 | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'metadata/md5-cache/sci-electronics/iverilog-9999') diff --git a/metadata/md5-cache/sci-electronics/iverilog-9999 b/metadata/md5-cache/sci-electronics/iverilog-9999 index f8f97ce3aa7f..e12eb7b11a75 100644 --- a/metadata/md5-cache/sci-electronics/iverilog-9999 +++ b/metadata/md5-cache/sci-electronics/iverilog-9999 @@ -1,6 +1,6 @@ -BDEPEND=>=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.1:1.16 >=sys-devel/automake-1.15.1:1.15 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4 >=dev-vcs/git-1.8.2.1[curl] +BDEPEND=dev-util/gperf sys-devel/bison sys-devel/flex >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.1:1.16 >=sys-devel/automake-1.15.1:1.15 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4 >=dev-vcs/git-1.8.2.1[curl] DEFINED_PHASES=install prepare unpack -DEPEND=dev-util/gperf sys-devel/bison sys-devel/flex sys-libs/readline:= sys-libs/zlib +DEPEND=sys-libs/readline:= sys-libs/zlib DESCRIPTION=A Verilog simulation and synthesis tool EAPI=7 HOMEPAGE=http://iverilog.icarus.com https://github.com/steveicarus/iverilog @@ -9,5 +9,5 @@ LICENSE=LGPL-2.1 PROPERTIES=live RDEPEND=sys-libs/readline:= sys-libs/zlib SLOT=0 -_eclasses_=autotools 7d999b62b8749fad43fff00620cedf47 git-r3 3e7ec3d6619213460c85e2aa48398441 libtool f143db5a74ccd9ca28c1234deffede96 multilib 2477ebe553d3e4d2c606191fe6c33602 toolchain-funcs 605c126bed8d87e4378d5ff1645330cb -_md5_=b3a351adbc57894edfe4efa07f656ae6 +_eclasses_=autotools 7d999b62b8749fad43fff00620cedf47 git-r3 3e7ec3d6619213460c85e2aa48398441 libtool f143db5a74ccd9ca28c1234deffede96 multilib 98584e405e2b0264d37e8f728327fed1 toolchain-funcs 605c126bed8d87e4378d5ff1645330cb +_md5_=ff154232ba7c8d2d31948f27debaf354 -- cgit v1.2.3