From 40aaaa64e86ba6710bbeb31c4615a6ce80e75e11 Mon Sep 17 00:00:00 2001 From: V3n3RiX Date: Wed, 28 Apr 2021 20:21:43 +0100 Subject: gentoo resync : 28.04.2021 --- metadata/md5-cache/sci-electronics/iverilog-9999 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'metadata/md5-cache/sci-electronics/iverilog-9999') diff --git a/metadata/md5-cache/sci-electronics/iverilog-9999 b/metadata/md5-cache/sci-electronics/iverilog-9999 index 3d4cf885182f..f80ddc8d838b 100644 --- a/metadata/md5-cache/sci-electronics/iverilog-9999 +++ b/metadata/md5-cache/sci-electronics/iverilog-9999 @@ -1,4 +1,4 @@ -BDEPEND=dev-util/gperf sys-devel/bison sys-devel/flex >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.2-r1:1.16 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4 >=dev-vcs/git-1.8.2.1[curl] +BDEPEND=dev-util/gperf sys-devel/bison sys-devel/flex sys-devel/gnuconfig >=app-portage/elt-patches-20170815 || ( >=sys-devel/automake-1.16.2-r1:1.16 ) >=sys-devel/autoconf-2.69 >=sys-devel/libtool-2.4 >=dev-vcs/git-1.8.2.1[curl] DEFINED_PHASES=install prepare unpack DEPEND=sys-libs/readline:= sys-libs/zlib DESCRIPTION=A Verilog simulation and synthesis tool @@ -8,5 +8,5 @@ LICENSE=LGPL-2.1 PROPERTIES=live RDEPEND=sys-libs/readline:= sys-libs/zlib SLOT=0 -_eclasses_=autotools 4ba6c345bf49883c84d5fa5c9bf40c0b git-r3 3e7ec3d6619213460c85e2aa48398441 libtool f143db5a74ccd9ca28c1234deffede96 multilib d410501a125f99ffb560b0c523cd3d1e toolchain-funcs 24921b57d6561d87cbef4916a296ada4 +_eclasses_=autotools 9e63f92c2a5d867fea55ecb160c7d354 git-r3 b8e8c92aa5fe8df7187e466138eb4e52 gnuconfig 9f91b4b0c84e734a87492d4293f03de5 libtool f143db5a74ccd9ca28c1234deffede96 multilib d410501a125f99ffb560b0c523cd3d1e toolchain-funcs 24921b57d6561d87cbef4916a296ada4 _md5_=53fe7f5f4565527a26b28a22c2a45c7c -- cgit v1.2.3